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Outside Research
Sun, May 01, 2016
A Scalable Flash-Based Hardware Architecture for the Hierarchical Temporal Memory Spatial Pooler
This Master’s thesis presents a scalable flash-based storage processor unit called Flash-HTM (FHTM), which utilizes Hierarchical Temporal Memory learning algorithms. FHTM is designed to scale with increasing model complexity. As validation, the author evaluates a mathematical model of the hardware against the MNIST dataset, yielding a 91.98% classification accuracy.
Lennard G. Streat
Fri, Apr 01, 2016
CLAASIC: a Cortex-Inspired Hardware Accelerator
This paper explores a hardware implementation for the HTM sequence memory (in the paper they use an older term, the “Cortical Learning Algorithm” to refer to the sequence memory). The paper hypothesizes a structure that is not application dependent and performs fully unsupervised continuous learning.
V. Puente and J.A. Gregorio